[Talon]

Originally Posted by ipaqgeek

Even with NAND you need an address, whether it is latched on the data lines or on their own address pins. With my proposal NO ADDRESS IS EVER NEEDED. You are simply doing a core-dump of the RAM into ROM, and then a core dump of ROM back into RAM. There is no random access. It requires no address muxing. The writing process is therefore greatly simplified and accelerated. As far as I know E^2 and FlashROMs have never been used this way.

Serial EEPROMS work that way. I suppose you could put 32 in parallel on the same die to get the effect you are talking about.

Originally Posted by ipaqgeek

For a 512 MB Flash you break it into 32 individual circuits of 16Mb. Throw a bus on the front and mux out the data streams (not muxing the addresses, because there are no addresses) with some SRAM cache on the front to integrate the sub-dies altogether and you increased your speed by 32X.

OK, I see what you mean. However I'm not sure if the PDA market alone is sufficent to cover the cost of developing a whole new type of memory chip which is so inflexible in it's use. You would need more markets to make such a device cheap enough to use, phone based systems are using the expensive mobile SDRAM to cut down power but probably wou'd have space for extra devices like this.
Also with your idea there would be no way to even out the wear, you would be writing the whole RAM into the whole flash each time. That may or may not be a life time issue.
Finally this backup flash would have to be in addition to any filestore flash, you would need to have two types of flash in the system. Generally it's a lot cheaper (and smaller) to just use one type and make it large enough for both uses.


Basically technically it sounds like a good idea but I don't think the economics are there to support it unless there are other markets or things move in a different direction.

Originally Posted by ipaqgeek

The Shadow ROM I'm proposing doesn't operate the same way you're talking about. It's just a core-dump of memory. No address muxing needed of any kind. [....]. We're talking about a major simplification of the peripheral logic circuitry. It can be made to go much faster with less silicon because the logic required to simply transfer core dumps in and out is so minimal.

The extra logic around a large flash die is tiny next to the size of the storage array. It may simplify the logic part of the design to remove it but it will have virtually no impact on cost.
Also the logic is not the slow point in the device, it's the flash array.
The only way the logic becomes the slow point is if you build enough sram in the device to buffer the maximum amount of data you want to store at one time (in this case the whole flash array). And even then you still have to wait for the flash access to finish before it's safe to switch the power off.
Fast SRAM is very expensive so adding that much just isn't an option.
For comparison a 512MByte NAND flash will have 2kbits of sram buffer.

Originally Posted by ipaqgeek

Very interesting. I guess it makes sense that it would have built-in error checking, seeing that it has a limited number of writes. If I recall correctly, Flash chips normally work faster after a few months of use, but they can also go the other direction - it can get worse.

You name it, they can do it. I've seen them output the wrong data unless read at 1/2 the rated speed. If you programmed them with the same data a second time they worked correctly. That was due to the internal erase timing being too optimistic and not fully erasing the cells, some cells were still half programed and the sense amplifiers needed longer to stabalise. That took a while to track down.

[Talon]

Originally Posted by ipaqgeek

Even with NAND you need an address, whether it is latched on the data lines or on their own address pins. With my proposal NO ADDRESS IS EVER NEEDED. You are simply doing a core-dump of the RAM into ROM, and then a core dump of ROM back into RAM. There is no random access. It requires no address muxing. The writing process is therefore greatly simplified and accelerated. As far as I know E^2 and FlashROMs have never been used this way.

Serial EEPROMS work that way. I suppose you could put 32 in parallel on the same die to get the effect you are talking about.

Originally Posted by ipaqgeek

For a 512 MB Flash you break it into 32 individual circuits of 16Mb. Throw a bus on the front and mux out the data streams (not muxing the addresses, because there are no addresses) with some SRAM cache on the front to integrate the sub-dies altogether and you increased your speed by 32X.

OK, I see what you mean. However I'm not sure if the PDA market alone is sufficent to cover the cost of developing a whole new type of memory chip which is so inflexible in it's use. You would need more markets to make such a device cheap enough to use, phone based systems are using the expensive mobile SDRAM to cut down power but probably wou'd have space for extra devices like this.
Also with your idea there would be no way to even out the wear, you would be writing the whole RAM into the whole flash each time. That may or may not be a life time issue.
Finally this backup flash would have to be in addition to any filestore flash, you would need to have two types of flash in the system. Generally it's a lot cheaper (and smaller) to just use one type and make it large enough for both uses.


Basically technically it sounds like a good idea but I don't think the economics are there to support it unless there are other markets or things move in a different direction.

Originally Posted by ipaqgeek

The Shadow ROM I'm proposing doesn't operate the same way you're talking about. It's just a core-dump of memory. No address muxing needed of any kind. [....]. We're talking about a major simplification of the peripheral logic circuitry. It can be made to go much faster with less silicon because the logic required to simply transfer core dumps in and out is so minimal.

The extra logic around a large flash die is tiny next to the size of the storage array. It may simplify the logic part of the design to remove it but it will have virtually no impact on cost.
Also the logic is not the slow point in the device, it's the flash array.
The only way the logic becomes the slow point is if you build enough sram in the device to buffer the maximum amount of data you want to store at one time (in this case the whole flash array). And even then you still have to wait for the flash access to finish before it's safe to switch the power off.
Fast SRAM is very expensive so adding that much just isn't an option.
For comparison a 512MByte NAND flash will have 2kbits of sram buffer.

Originally Posted by ipaqgeek

Very interesting. I guess it makes sense that it would have built-in error checking, seeing that it has a limited number of writes. If I recall correctly, Flash chips normally work faster after a few months of use, but they can also go the other direction - it can get worse.

You name it, they can do it. I've seen them output the wrong data unless read at 1/2 the rated speed. If you programmed them with the same data a second time they worked correctly. That was due to the internal erase timing being too optimistic and not fully erasing the cells, some cells were still half programed and the sense amplifiers needed longer to stabalise. That took a while to track down.

[Pete Wilson]

For those of you who never knew it, the Newton solved these issues.

My MP 2100 has 4MB RAM (and it was an upgrade from 1MB) but lots of Flash.

I left it unplugged for a year. I plugged it in, turned it on, pulled up a note recording a serial # in five clicks.

While everything is in Flash, code is paged into RAM on a tiny method / object basis, so execution speed is not greatly hampered by having large programs in Flash.

The OS and Apps are written in an object oriented environment that allows easy extension and modification by just replacing the portion of a system that you need to modify, meaning you use minimal RAM for additional functionality.

Someday, I hope my iPAQ is as good as my MessagePad from 1996.

[ipaqgeek]

I responded to this a couple of days ago, but it looks like my response never got posted.

1) You simply cannot have large volumes of RAM in a PDA (greater than 128Mb) because it drains the battery too quickly while the PDA is off. For example: if you use up the battery, then that night if forget to plug in your PDA with 256Mb DRAM then you could loose everything stored in RAM - registry settings, preferences, program setups, etc.

2) FlashROM is vastly inferior to RAM when it comes to speed, robustness and lifetime, making it unsuitable as a memory from which to run programs.

I do NOT see how this situation can improve at all over the next 5-10 years unless a totally different memory scheme is developed. As far as I know, my "Core-Dump FlashROM" solution is the only one that viably resolves these two issues. To summarize it, that solution is to store everything in RAM, and core-dump the RAM contents back and forth from FlashROM a couple of times per day as determined by a memory management program while the PDA is turned off, during which times all power is shut off to the RAM.

What's more, this solution could be partially implemented on all existing hardware with just a memory management program by partitioning off a small part of the FlashROM, maybe only 1Mb to be dedicated for doing this for the registry and other user and program settings. Although this wouldn't allow you to shut off power to the RAM, it would however protect your most valuable data.

For full implementation which would enable GB and larger RAM capacities, it will require a new kind of FlashROM - similar to Serial E^2 but even simpler, designed in a massively parrallel fashion without the need for any address multiplexing. There have been no arguments suggested so far that are show-stoppers to this solution (see below).

If anyone else has some solutions please provide them.. but what we have sucks, and I see no other way to solve the two problems I pointed out above.

Originally Posted by Talon

However I'm not sure if the PDA market alone is sufficent to cover the cost of developing a whole new type of memory chip which is so inflexible in it's use.

Inflexible? We're talking about essentially turning RAM into a nonvolatile memory. This is the mother-lode of all memory qualities and features. This is what MRAM, OUM, FRAM, etc. have been unsuccessfully trying to do, but if the right person caught the vision they could spit this out of their fabs in 12 months and it would do everything those other technologies are attempting: RAM like performance with non-volatile properties.

Originally Posted by Talon

mobile phones... probably wou'd have space for extra devices like this.

We're not talking a lot of hardware. A couple of extra chips.

Originally Posted by Talon

Also with your idea there would be no way to even out the wear, you would be writing the whole RAM into the whole flash each time. That may or may not be a life time issue.

You're writing to each bit no more than a few times/day. That puts your lifetime in the range of 100's of years.

Originally Posted by Talon

Finally this backup flash would have to be in addition to any filestore flash, you would need to have two types of flash in the system.

No you wouldnt, you'd only need Core-dump-FlashROM, which makes RAM act like a non-volatile memory. You wouldn't need anything else. Filestore would be in RAM with everything else, and core-dumped to FlashROM at strategic time intervals.

Originally Posted by Talon

Basically technically it sounds like a good idea but I don't think the economics are there to support it unless there are other markets or things move in a different direction.

See above. It serves EVERY mobile market.

Originally Posted by Talon

The extra logic around a large flash die is tiny next to the size of the storage array. It may simplify the logic part of the design to remove it but it will have virtually no impact on cost.

I'm sure you'd agree how wrong that statement is if you thought about it. Chip cost is driven almost entirely by yield, and yield is influenced by chip complexity more than any other factor because the design rules are locked in. If design rules are followed then nearly all array yield problems can be fixed via process changes - not so with periphery yield problems, and that's where the complexity is, and with Core-Dump-FlashROM there is very little periphery, and no expected timing issues.

Originally Posted by Talon

Also the logic is not the slow point in the device, it's the flash array.

Yes, you're right, nearly all the speed benefit comes from massively muxing out the data streams, so much so that you wouldn't need much SRAM.

Originally Posted by Talon

I've seen them output the wrong data unless read at 1/2 the rated speed. If you programmed them with the same data a second time they worked correctly. That was due to the internal erase timing being too optimistic and not fully erasing the cells, some cells were still half programed and the sense amplifiers needed longer to stabalise. That took a while to track down.

Ughhh. You're bringing back bad memories. I left that industry 5 years ago because I got tired of being the point man for tracking down such problems, and they don't pay enough for that kind of work. I paid my dues for nearly a dozen years as a Yield / Process Integration Engineer, and nothing could make me go back to it. I hope you've been able to work your way into management, because you can't do the real troubleshooting for long before you burn out like I did after a dozen years of it.

[abarry]

What is the advantage of storing programs in RAM? Would it slow down the PPC? Why not use the storage card instead?

What is the default installation folder? Is this the same as RAM? If I choose not to use it I am given the option of Main Memory (is this ROM?) or Storage (what's this?) besides the storae card.

Please enlighten me.

Thanks

Atul

[DinarSoft]

Originally Posted by abarry

What is the advantage of storing programs in RAM? Would it slow down the PPC? Why not use the storage card instead?

What is the default installation folder? Is this the same as RAM? If I choose not to use it I am given the option of Main Memory (is this ROM?) or Storage (what's this?) besides the storae card.

Please enlighten me.

Thanks

Atul

The advantage from having a program in the main memory will be the loading time (it will load faster).
However having less RAM available will slow down the whole device.

Some programs also need to be installed in RAM (if they are set to start with the system).
External cards tend to take some time to boot (when you soft reset) and in some devices the system takes less time to boot than the external card and that makes the system unable to run programs from the external card right after booting (this happens with some devices/cards and only is a problem for programs you want to start with the system)


Your default installation path (main memory) will direct the programs to be installed in "\Program Files" (which is RAM).

Main memory is RAM
storage is ROM (built-in-storage)