Toshiba's 1GHz 65nm Media Processor

[Suhit Gupta]

http://www.theregister.co.uk/2005/08/17/toshiba_mep_h1/

"Toshiba today announced what it claims is the world's first 1GHz configurable microprocessor - and probably the first of its kind to be fabbed at 65nm. The MeP (Media Embedded Processor) chip family is aimed at digital consumer electronics kit and is designed to support a high level of customisation - including the addition of new instructions - prior to manufacturing. The architecture also supports the addition of embedded memory... Toshiba said it will tout the part as the foundation for future "digital media products that require processing of large volume of image and audio data", such as digital TVs and DVD recorders. It plans to use the MeP line in its own products and to license the technology to third-parties."

For those of you that have studied computer architecture, in school or elsewhere (I recommend the Patterson & Hennessy books), will appreciate the following - a new nine-stage instruction pipeline, extended from the previous five-stage pipeline. The h1, founded upon a 32-bit RISC core, also features an instruction re-order buffer, and multiple MePs can be connected to form a single system-on-a-chip. Anyways, I am happy to hear that Toshiba has manufacured this new chip. It will probably make embedded devices so much faster.

[Suhit Gupta]

http://www.theregister.co.uk/2005/08/17/toshiba_mep_h1/

"Toshiba today announced what it claims is the world's first 1GHz configurable microprocessor - and probably the first of its kind to be fabbed at 65nm. The MeP (Media Embedded Processor) chip family is aimed at digital consumer electronics kit and is designed to support a high level of customisation - including the addition of new instructions - prior to manufacturing. The architecture also supports the addition of embedded memory... Toshiba said it will tout the part as the foundation for future "digital media products that require processing of large volume of image and audio data", such as digital TVs and DVD recorders. It plans to use the MeP line in its own products and to license the technology to third-parties."

For those of you that have studied computer architecture, in school or elsewhere (I recommend the Patterson & Hennessy books), will appreciate the following - a new nine-stage instruction pipeline, extended from the previous five-stage pipeline. The h1, founded upon a 32-bit RISC core, also features an instruction re-order buffer, and multiple MePs can be connected to form a single system-on-a-chip. Anyways, I am happy to hear that Toshiba has manufacured this new chip. It will probably make embedded devices so much faster.